Design of CRC circuit for 5G system using VHDL

نویسندگان

چکیده

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) integrate in field-programmable gate array (FPGA) suitable kit a code. The between designed came from the of data size according polynomials requirements conditions since there are huge system that required divide it method and then implemented circuit. CRC code as polar short low density parity (LDPC) is proposed new radio (NR) systems, properties divided cod make particularly useful for codes higher rate longer lengths, rates small length an error detection method. encoder (transmitter side) decoder (receiver have been VHDL. Xilinx ISE 14.3 simulator, where test bench simulation results give expected simulator decoding scheme so ZYNQ FPGA kit.

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ژورنال

عنوان ژورنال: Bulletin of Electrical Engineering and Informatics

سال: 2023

ISSN: ['2302-9285']

DOI: https://doi.org/10.11591/eei.v12i4.4598